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ADP3212A, NCP3218A 7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller
The APD3212A/NCP3218A is a highly efficient, multi-phase, synchronous buck switching regulator controller. With its integrated drivers, the APD3212A/NCP3218A is optimized for converting the notebook battery voltage into the core supply voltage required by high performance Intel processors. An internal 7-bit DAC is used to read a VID code directly from the processor and to set the CPU core voltage to a value within the range of 0.3 V to 1.5 V. The APD3212A/ NCP3218A is programmable for 1-, 2-, or 3-phase operation. The output signals ensure interleaved 2- or 3-phase operation. The APD3212A/NCP3218A uses a multimode architecture run at a programmable switching frequency and optimized for efficiency depending on the output current requirement. The APD3212A/NCP3218A switches between single- and multi-phase operation to maximize efficiency with all load conditions. The chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The APD3212A/NCP3218A also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power-good output. The IC supports On-The-Fly (OTF) output voltage changes requested by the CPU. The APD3212A/NCP3218A are specified over the extended commercial temperature range of -40C to 100C. The ADP3212A is available in a 48-lead QFN 7x7mm 0.5mm pitch package. The NCP3218A is available in a 48-lead QFN 6x6mm 0.4mm pitch package. Except for the packages, the APD3212A/NCP3218A are identical. APD3212A/NCP3218A are Halogen-Free, Pb-Free and RoHS compliant.
Features http://onsemi.com
QFN48 CASE 485AJ 1 48 QFN48 CASE 485AN 1 48
MARKING DIAGRAM
1
xxP321xA AWLYYWWG
= Specific Device Code (ADP3212A or NCP3218A) A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package
xxx
* Single-Chip Solution * Fully Compatible with the Intel(R) IMVP-6.5t * Selectable 1-, 2-, or 3-Phase Operation with Up to * * * * * *
Specifications 1 MHz per Phase Switching Frequency Phase 1 and Phase 2 Integrated MOSFET Drivers Input Voltage Range of 3.3 V to 22 V Guaranteed 8 mV Worst-Case Differentially Sensed Core Voltage Error Over Temperature Automatic Power-Saving Mode Maximizes Efficiency with Light Load During Deeper Sleep Operation Active Current Balancing Between Output Phases Independent Current Limit and Load Line Setting Inputs for Additional Design Flexibility
* Built-In Power-Good Blanking Supports Voltage
1.5 V Output
* 7-Bit, Digitally Programmable DAC with 0.3 V to
Identification (VID) On-The-Fly (OTF) Transients
* Short-Circuit Protection with Programmable Latchoff * * * * *
Delay Clock Enable Output Delays the CPU Clock Until the Core Voltage is Stable Output Power or Current Monitor Options 48-Lead QFN 7x7mm (ADP3212A), 48-Lead QFN 6x6mm (NCP3218A) These are Pb-Free Devices Fully RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 33 of this data sheet.
Applications
* Notebook Power Supplies for Next-Generation Intel
Processors
(c) Semiconductor Components Industries, LLC, 2010
June, 2010 - Rev. 0
1
Publication Order Number: ADP3212A/D
ADP3212A, NCP3218A
PIN ASSIGNMENT
VID0 VID1 VID2 VID3 VID4 VID5 VID6 PSI DPRSLP PH0 PH1 VCC EN PWRGD IMON CLKEN FBRTN FB COMP TRDET VARFREQ VRTT TTSNS GND 1 ADP3212A NCP3218A (top view) BST1 DRVH1 SW1 SWFB1 PVCC DRVL1 PGND DRVL2 SWFB2 SW2 DRVH2 BST2 GND VCC EN UVLO Shutdown and Bias VEA - + CSREF - + IREF RPM RT RAMP LLINE CSREF CSSUM CSCOMP ILIM OD3 PWM3 SWFB3 RPM RT RAMP VARFREQ BST1 Oscillator Current Balancing Circuit OVP Driver Logic DRVH1 SW1 PVCC DRVL1 PGND BST2 DRVH2 SW2 PVCC Number of Phases OCP Shutdown Delay Current Limit Circuit Soft Transient Delay CLKEN Start Up Delay Delay Disable Thermal Throttle Control Soft Start REF DRVL2 PGND OD3 PWM3 PSI and DPRSLP Logic Current Current Monitor Monitor + - PSI DPRSLP IMON CSREF CSSUM CSCOMP ILIM TTSENSE VRTT TRDET COMP FB + REF LLINE SWFB1 SWFB2 SWFB3 PH0 PH1 DAC + 200 mV CSREF - + - + DAC - 300 mV PWRGD Open Drain CLKEN Open Drain Precision Reference VID DAC PWRGD Start Up Delay + S TRDET Generator + S_ 1.55 V PWRGD CLKEN FBRTN DAC IREF 2 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Figure 1. Functional Block Diagram http://onsemi.com
ADP3212A, NCP3218A
ABSOLUTE MAXIMUM RATINGS
Parameter VCC, PVCC1, PVCC2 FBRTN, PGND1, PGND2 BST1, BST2, DRVH1, DRVH2 DC t < 200 ns BST1 to PVCC, BST2 to PVCC DC t < 200 ns BST1 to SW1, BST2 to SW2 SW1, SW2 DC t < 200 ns DRVH1 to SW1, DRVH2 to SW2 DRVL1 to PGND1, DRVL2 to PGND2 DC t < 200 ns RAMP (in Shutdown) All Other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (qJA) 2-Layer Board Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 to +6.0 -0.3 to +0.3 -0.3 to +28 -0.3 to +33 -0.3 to +22 -0.3 to +28 -0.3 to +6.0 -1.0 to +22 -6.0 to +28 -0.3 to +6.0 -0.3 to +6.0 -5.0 to +6.0 -0.3 to +22 -0.3 to +6.0 -65 to +150 -40 to +100 125 30.5 300 260 Unit V V V
V
V V
V V
V V C C C C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
PIN ASSIGNMENT
Pin No. 1 2 3 4 5 6 7 8 Mnemonic EN PWRGD IMON CLKEN FBRTN FB COMP TRDET Description Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT low, and pulls CLKEN high. Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside of the VID DAC defined range. Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to FBRTN sets the current monitor gain. Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to lock to the external clock. Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground return for the VID DAC and the voltage error amplifier blocks. Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier. Voltage Error Amplifier Output and Frequency Compensation Point. Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive load transients at high frequencies, this circuit optimally positions the maximum and minimum output voltage into a specified loadline window. Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code. Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator temperature at the remote sensing point exceeded a set alarm threshold level.
9 10
VARFREQ VRTT
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ADP3212A, NCP3218A
PIN ASSIGNMENT
Pin No. 11 Mnemonic TTSNS Description Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip. Analog and Digital Signal Ground. This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground. RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn-on threshold voltage. Multi-phase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device when operating in multi-phase PWM mode threshold of the converter. PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets the slope of the internal PWM stabilizing ramp used for phase-current balancing. Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is connected to this pin to set the load line slope. Current Sense Reference Input. This pin must be connected to the common point of the output inductors. The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop transient control of the converter output voltage. Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currents to provide total current information. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the current-sense amplifier and the positioning loop response time. Current Limit Setpoint. An external resistor from this pin to CSCOMP sets the current limit threshold of the converter. Multi-phase Output Disable Logic Output. This pin is actively pulled low when the APD3212A/NCP3218A enters single-phase mode or during shutdown. Connect this pin to the SD inputs of the Phase-3 MOSFET drivers. Logic-Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the ADP3611. Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should be left open for 1 or 2 phase configuration. High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage while the high-side MOSFET is on. High-Side Gate Drive Output for Phase 2. Current Return for High-Side Gate Drive for phase 2. Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should be left open for 1 phase configuration. Low-Side Gate Drive Output for Phase 2. Low-Side Driver Power Ground Low-Side Gate Drive Output for Phase 1. Power Supply Input/Output of Low-Side Gate Drivers. Current Balance Input for phase 1. Input for measuring the current level in phase 1. Current Return For High-Side Gate Drive for phase 1. High-Side Gate Drive Output for Phase 1. High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage while the high-side MOSFET is on. Power Supply Input/Output of the Controller. Phase Number Configuration Input. Connect to VCC for 3 phase configuration. Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for multi-phase configuration. Deeper Sleep Control Input. Power State Indicator Input. Pulling this pin to GND forces the APD3212A/NCP3218A to operate in single-phase mode. Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3 V to 1.5 V (see Table 3).
12 13 14 15 16 17 18
GND IREF RPM RT RAMP LLINE CSREF
19 20 21 22
CSSUM CSCOMP ILIM OD3
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 to 48
PWM3 SWFB3 BST2 DRVH2 SW2 SWFB2 DRVL2 PGND DRVL1 PVCC SWFB1 SW1 DRVH1 BST1 VCC PH1 PH0 DPRSLP PSI VID6 to VID0
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ADP3212A, NCP3218A
ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = -40C to 100C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign. Parameter FB, LLINE Voltage Range (Note 2) FB, LLINE Offset Voltage (Note 2) LLINE Bias Current FB Bias Current LLINE Positioning Accuracy COMP Voltage Range (Note 2) COMP Current Symbol VFB, VLLINE VOSVEA ILLINE IFB VFB - VVID VCOMP ICOMP COMP = 2.0 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF Non-inverting unit gain configuration, RFB = 1 kW See VID table VFB - VVID Measured on FB (includes offset), relative to VVID VVID = 0.5000 V to 1.5000 V, T = -10C to 100C VVID = 0.5000 V to 1.5000 V, T = -40C to 100C VVID = 0.3000 V to 0.4875 V, T = -10C to 100C VVID = 0.3000 V to 0.4875 V, T = -40C to 100C 0 Measured on FB relative to VVID, LLINE forced 80 mV below CSREF Conditions Relative to CSREF = VDAC Relative to CSREF = VDAC Min -200 -0.5 -100 -1.0 -77.5 0.85 -0.75 6.0 -80 Typ Max +200 +0.5 +100 +1.0 -82.5 4.0 Units mV mV nA mA mV V mA VOLTAGE CONTROL - VOLTAGE ERROR AMPLIFIER (VEAMP)
COMP Slew Rate
SRCOMP
V/ms 15 -20 20 MHz
Gain Bandwidth (Note 2) VID DAC VOLTAGE REFERENCE VDAC Voltage Range (Note 2) VDAC Accuracy
GBW
1.5
V mV
-7.5 -9.0 -9.0 -10 -1.0
+7.5 +9.0 +9.0 +10 +1.0 0.001 1.100 200 1.4 60 0.0625 0.25 1.0 0.4 1.0 -90 -200 -360 250 250 mA mV mV LSB % V ms ms ms LSB/ ms
VDAC Differential Non-linearity (Note 2) VDAC Line Regulation VDAC Boot Voltage Soft-Start Delay (Note 2) Soft-Start Time Boot Delay VDAC Slew Rate (Note 2) VFB VBOOTFB tDSS tSS tBOOT VCC = 4.75 V to 5.25 V Measured during boot delay period Measured from EN pos edge to FB = 50 mV Measured from FB = 50 mV to FB settles to 1.1 V within 5% Measured from FB settling to 1.1 V within 5% to CLKEN neg edge Soft-Start Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit Non-LSB VID step, DPRSLP = L, Fast C4 Exit LSB VID step, DVID transition GPU Mode, Non-LSB VID step, Fast Entry/Exit IFBRTN VUVCSREF VOVCSREF Relative to nominal VDAC voltage Relative to nominal VDAC voltage, T = -10C to 100C T = -40C to 100C
FBRTN Current CSREF Undervoltage Threshold CSREF Overvoltage Threshold
VOLTAGE MONITORING and PROTECTION - POWER GOOD -240 150 140 -300 200 200
1. 2. 3. 4.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested. Based on bench characterization data. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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ADP3212A, NCP3218A
ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = -40C to 100C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign. Parameter CSREF Crowbar Voltage Threshold CSREF Reverse Voltage Threshold PWRGD Low Voltage PWRGD High, Leakage Current PWRGD Startup Delay PWRGD Latchoff Delay PWRGD Propagation Delay (Note 3) Crowbar Latchoff Delay (Note 2) PWRGD Masking Time CSREF Soft-Stop Resistance CSSUM, CSREF Common-Mode Range (Note 2) CSSUM, CSREF Offset Voltage VOSCSA Symbol VCBCSREF VRVCSREF Conditions Relative to FBRTN Relative to FBRTN, latchoff mode CSREF is falling CSREF is rising IPWRGD(SINK) = 4 mA VPWRDG = 5.0 V Measured from CLKEN neg edge to PWRGD pos edge Measured from Out-off-Good-Window event to Latchoff (switching stops) Measured from Out-off-Good-Window event to PWRGD neg edge Measured from Crowbar event to latchoff (switching stops) Triggered by any VID change or OCP event EN = L or latchoff condition Voltage range of interest CSREF - CSSUM, TA = 25C TA = -10C to 85C TA = -40C to 85C 0 -0.5 -1.7 -1.9 -50 -2.0 Voltage range of interest ICSCOMPsource ICSCOMPsink CSCOMP Slew Rate (Note 2) CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF CCSCOMP = 10 pF, CSREF = VDAC, Open loop configuration CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF GBWCSA Non-inverting unit gain configuration RFB = 1 kW 0.05 -750 1.0 9.0 9.0 200 200 100 70 2.0 +0.5 +1.7 +1.9 +50 +2.0 2.0 Min 1.5 Typ 1.55 Max 1.6 Units V mV -10 250 1.0 mV mA ms ms ns ns ms W V mV VOLTAGE MONITORING and PROTECTION - POWER GOOD
-350
-300 -75 85
VPWRGD IPWRGD TSSPWRGD TLOFFPWRGD TPDPWRGD TLOFFCB
CURRENT CONTROL - CURRENT-SENSE AMPLIFIER (CSAMP)
CSSUM Bias Current CSREF Bias Current CSCOMP Voltage Range (Note 2) CSCOMP Current
IBCSSUM IBCSREF
nA mA V mA mA V/ms
20 -20 20 MHz
Gain Bandwidth (Note 2)
CURRENT MONITORING and PROTECTION CURRENT REFERENCE IREF Voltage CURRENT LIMITER (OCP) Current Limit (OCP) Threshold VLIMTH Measured from CSCOMP to CSREF, RLIM = 1.5 kW, 3-ph configuration, PSI = H 3-ph configuration, PSI = L 2-ph configuration, PSI = H 2-ph configuration, PSI = L 1-ph configuration Measured from OCP event to PWRGD de-assertion mV -80 -22 -80 -35 -75 -90 -30 -90 -45 -90 150 -100 -38 -100 -55 -105 ms VREF RREF = 80 kW to set IREF = 20 mA 1.55 1.6 1.65 V
Current Limit Latchoff Delay 1. 2. 3. 4.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested. Based on bench characterization data. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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ADP3212A, NCP3218A
ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = -40C to 100C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign. Parameter CURRENT MONITOR Current Gain Accuracy IMON/ILIM Measured from ILIM to IMON ILIM = -20 mA ILIM = -10 mA ILIM = -5 mA Relative to FBRTN, ILIMP = -30 mA VARFREQ = high, RT = 125 kW, VVID = 1.5000 V VARFREQ = low See also VRT(VVID) formula Operation of interest TA = +25C, VVID = 1.2000 V RT = 72 kW RT = 120 kW RT = 180 kW EN = high, IRAMP = 60 mA EN = low EN = high EN = low, RAMP = 19 V VRAMP - VCOMP VVID = 1.2 V, RT = 215 kW See also IRPM(RT) formula VCOMP - (1 + VRPMTH) Relative to COMP sampled TCLK time earlier 3-phase configuration 2-phase configuration 1-phase configuration Relative to COMP sampled TCLK time earlier 3-phase configuration 2-phase configuration 1-phase configuration VLTRDET IHTRDET VSW(X)CM RSW(X) VDCM(SW1) tOFFMSKD Logic low, ITRDETsink = 4 mA Logic high, VTRDET = VCC Operation of interest for current sensing SWX = 0 V, SWFB = 0 V DCM mode, DPRSLP = 3.3 V Measured from DRVH1 neg edge to DRVH1 pos edge at operation max frequency -600 20 35 -3.0 600 3.7 3.6 3.5 1.0 4.0 4.0 4.0 4.3 4.4 4.5 1.16 - Symbol Conditions Min Typ Max Units
IMON Clamp Voltage RT Voltage
VMAXMON VRT
V V
PULSE WIDTH MODULATOR - CLOCK OSCILLATOR 1.125 0.9 0.3 1.25 1.0 1.375 1.1 3.0
PWM Clock Frequency Range (Note 2) PWM Clock Frequency
fCLK fCLK
MHz kHz
900 700 300 0.9 1.0 -1.0
1200 800 400 1.0 VIN
1500 900 500 1.1 100 +1.0
RAMP GENERATOR RAMP Voltage RAMP Current Range (Note 2) PWM COMPARATOR PWM Comparator Offset (Note 2) RPM COMPARATOR RPM Current RPM Comparator Offset (Note 2) EPWM CLOCK SYNC Trigger Threshold (Note 2) mV 350 400 450 mV -450 -500 -600 30 300 3.0 +200 50 mV mA mV kW mV ns IRPM VOSRPM -5.5 3.0 mA mV VOSRPM 3.0 mV VRAMP IRAMP V mA
TRDET Trigger Threshold (Note 2)
TRDET Low Voltage (Note 2) TRDET Leakage Current SWITCH AMPLIFIER SW Common Mode Range (Note 2) SWFB Input Resistance SW ZCS Threshold Masked Off-Time
ZERO CURRENT SWITCHING COMPARATOR
1. 2. 3. 4.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested. Based on bench characterization data. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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ADP3212A, NCP3218A
ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = -40C to 100C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign. Parameter SYSTEM I/O BUFFERS VID[6:0], DPRSLP, PSI INPUTS Input Voltage Refers to driving signal level Logic low Logic high V = 0.2 V, VID[6:0], DPRSLP (active pulldown to GND) PSI (active pullup to VCC) Any VID edge to FB change 10% Refers to driving signal level Logic low Logic high 200 0.3 V Symbol Conditions Min Typ Max Units
2.0 1.0 -2.0
Input Current
mA
VID Delay Time (Note 2) VARFREQ Input Voltage
ns V
4.0 1.0
0.7
Input Current EN INPUT Input Voltage Refers to driving signal level Logic low Logic high EN = L or EN = H (static) 0.8 V < EN < 1.6 V (during transition) Refers to driving signal level Logic low Logic high
mA V
1.7 10 -70
0.5
Input Current PH1, PH0 INPUTS Input Voltage
nA mA V
2.0 1.0
0.5
Input Current CLKEN OUTPUT Output Low Voltage Output High, Leakage Current PWM3, OD3 OUTPUTS Output Voltage THERMAL MONITORING and PROTECTION TTSNS Voltage Range (Note 2) TTSNS Threshold TTSNS Hysteresis TTSNS Bias Current VRTT Output Voltage SUPPLY Supply Voltage Range Supply Current VCC OK Threshold VCC UVLO Threshold VCC Hysteresis (Note 2) HIGH-SIDE MOSFET DRIVER Pullup Resistance, Sourcing Current (Note 3) 1. 2. 3. 4. BST = PVCC VCCOK VCCUVLO VCC EN = high EN = 0 V VCC is rising VCC is falling 4.0 4.5 VVRTT TTSNS = 2.6 V Logic low, IVRTT(SINK) = 400 mA Logic high, IVRTT(SOURCE) = -400 mA VCC = 5.0 V, TTSNS is falling 0 2.45 50 -2.0 4.5 Logic low, ISINK = 400 mA Logic high, ISOURCE = -400 mA 4.0 Logic low, Isink = 4 mA Logic high, VCLKEN = VCC
mA 200 0.1 mV mA mV V V V mV 2.0 mA mV V V mA mA V V mV 3.3 W 500
60
10 5.0
500
5.0 2.5 95 10 5.0 2.55
5.5 7 10 4.4 4.15 250 1.25 10 50 4.5
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested. Based on bench characterization data. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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ADP3212A, NCP3218A
ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = -40C to 100C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign. Parameter HIGH-SIDE MOSFET DRIVER Pulldown Resistance, Sinking Current (Note 3) Transition Times Dead Delay Times trDRVH tfDRVH tpdhDRVH BST = PVCC BST = PVCC, CL = 3 nF, Figure 2 BST = PVCC, CL = 3 nF, Figure 2 BST = PVCC, Figure 2 T = -10C to 100C T = -40C to 100C EN = L (Shutdown) EN = H, no switching 28 0.8 15 13 32 1.0 200 0.88 0.65 trDRVL tfDRVL tpdhDRVL CL = 3 nF, Figure 2 CL = 3 nF, Figure 2 CL = 3 nF, Figure 2 T = -10C to 100C T = -40C to 100C DRVH = L, SW = 2.5 V T = -10C to 100C T = -40C to 100C EN = L (Shutdown) EN = H, no switching EN = L or EN = H and DRVL = H 5.0 85 85 15 14 11 12 250 250 1.6 1.0 170 7.0 10 2.0 35 31 36 50 10 W ns ns Symbol Conditions Min Typ Max Units
BST Quiescent Current LOW-SIDE MOSFET DRIVER Pullup Resistance, Sourcing Current (Note 3) Pulldown Resistance, Sinking Current (Note 3) Transition Times Propagation Delay Times
mA
2.8 1.7 35 35 30 40 300 450
W W ns ns
SW Transition Timeout
tTOSW
ns
SW Off Threshold PVCC Quiescent Current BOOTSTRAP RECTIFIER SWITCH On Resistance (Note 3) 1. 2. 3. 4.
VOFFSW
V mA
12
W
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested. Based on bench characterization data. Timing is referenced to the 90% and 10% points, unless otherwise noted.
IN tpdlDRVL DRVL tfDRVL tpdlDRVH
trDRVL
tpdhDRVH DRVH (WITH RESPECT TO SW)
trDRVH
tfDRVH
VTH
VTH
tpdhDRVL SW 1.0 V
Figure 2. Timing Diagram (Note 4) http://onsemi.com
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ADP3212A, NCP3218A
TEST CIRCUITS
7-BIT CODE 5V 48 3.3 V EN 1 PWRGD VID0 VID1 VID2 VID3 VID4 VID5 VID6 PSI DPRSLP PH1 PH2 VCC BST1 DRVH1
1 kW
IREF RPM RT RAMP LLINE CSREF CSSUM CSCOMP ILIM OD3 PWM3 SWFB3
IMON CLKEN FBRTN FB COMP TRDET VARFREQ VRTT TTSNS
SW1 SWFB1 PVCC DRVL1 ADP3212A PGND DRVL2 SWFB2 SW2
GND
DRVH2 BST2
80 kW 20 kW 100 nF
Figure 3. Closed-Loop Output Voltage Accuracy
5.0 V 37 VCC 7 5.0 V ADP3212A 37 VCC 20 39 kW 1 kW 1.0 V 12 GND V OS + 100 nF 19 18 CSSUM CSREF - DV + CSCOMP * 1.0 V 40 V 1.0 V 12 GND 18 CSREF CSCOMP 17 LLINE 10 kW 6 COMP
ADP3212A
FB
- +
VID DAC
DV FB + FB DV + DV * FB DV+0 mV
Figure 4. Current Sense Amplifier, VOS
Figure 5. Positioning Accuracy
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ADP3212A, NCP3218A
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20C to 100C, unless otherwise noted. 400 350 PER PHASE SWITCHING FREQUENCY (kHz) 300 250 200 150 100 50 0 0.25 0.50 0.75 1.00 RT = 187 kW 2 Phase Mode 1.25 VARFREQ = 0 V VARFREQ = 5 V SWITCHING FREQUENCY (kHz) 1000 VID = 1.4125 V VID = 1.2125 V
VID = 1.1 V VID = 0.8125 V VID = 0.6125 V 100
1.50
10
100 Rt RESISTANCE (kW)
1000
VID OUTPUT VOLTAGE (V)
Figure 6. Switching Frequency vs. VID Output Voltage in PWM Mode
Figure 7. Per Phase Switching Frequency vs. RT Resistance
Output Voltage
Output Voltage
1 PWRGD CLKEN EN 1: 0.5 V/div 2: 2 V/div 3: 5 V/div 4: 5 V/div 1 ms/div GPU Mode
1 PWRGD
2 3 4
2 3 4 EN 1: 0.5 V/div 2: 2 V/div 3: 5 V/div 4: 5 V/div 4 ms/div CPU Mode CLKEN
Figure 8. Startup in GPU Mode
Figure 9. Startup in CPU Mode
Output Voltage 1 2 EN CLKEN 4 1: 0.5 V/div 2: 2 V/div 3: 2 V/div 4: 2 V/div 200 ms/div 1 A Load PWRGD
3
Figure 10. Shutdown
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ADP3212A, NCP3218A
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20C to 100C, unless otherwise noted.
SW1 1 SW2 2 SW3 3
1 2
SW1 SW2
SW3 3
DPRSLP 4 1: 10 V/div 2: 10 V/div 3: 10 V/div 4: 2 V/div 4 ms/div 4
PSI 1: 10 V/div 2: 10 V/div 3: 10 V/div 4: 0.5 V/div 4 ms/div
Figure 11. DPRSLP Transition with PSI = High
Figure 12. PSI Transition with DPRSLP = Low
SW1 SW1 1 2 SW2 2 SW3 3 DPRSLP 4 4 1: 10 V/div 2: 10 V/div 3: 10 V/div 4: 2 V/div 4 ms/div PSI 1: 10 V/div 2: 10 V/div 3: 10 V/div 4 ms/div 4: 0.5 V/div SW3 1 SW2
3
Figure 13. DPRSLP Transition with PSI = High
Figure 14. PSI Transition with DPRSLP = Low
SW1 1 SW2 2 SW3 3 3 DPRSLP 4 1: 10 V/div 2: 10 V/div 3: 10 V/div 4: 2 V/div 4 ms/div 4 1: 10 V/div 2: 10 V/div 3: 10 V/div 4: 2 V/div DPRSLP 4 ms/div 2 SW3 1 SW2
SW1
Figure 15. DPRSLP Transition with PSI = Low
Figure 16. DPRSLP Transition with PSI = Low
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Theory of Operation
The APD3212A/NCP3218A combines multi-mode Pulse-Width Modulated (PWM) control and Ramp-Pulse Modulated (RPM) control with multi-phase logic outputs for use in single-, dual-phase, or triple-phase synchronous buck CPU core supply power converters. The internal 7-bit VID DAC conforms to the Intel IMVP-6.5 specifications. Multi-phase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling high currents in a single-phase converter would put too high of a thermal stress on system components such as the inductors and MOSFETs. The multimode control of the APD3212A/NCP3218A is a stable, high performance architecture that includes * Current and thermal balance between phases. * High speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors. * Minimized thermal switching losses due to lower frequency operation. * High accuracy load line regulation. * High current output by supporting 2-phase or 3-phase operation. * Reduced output ripple due to multi-phase ripple cancellation. * High power conversion efficiency with heavy and light loads. * Increased immunity from noise introduced by PC board layout constraints. * Ease of use due to independent component selection. * Flexibility in design by allowing optimization for either low cost or high performance.
Number of Phases
monitors the PWM outputs. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be active at a time, permitting overlapping phases.
Operation Modes
The number of operational phases can be set by the user. Tying the PH1 pin to the GND pin forces the chip into single-phase operation. Tying PH0 to GND and PH1 to VCC forces the chip into 2-phase operation. Tying PH0 and PH1 to VCC forces the chip in 3-phase operation. PH0 and PH1 should be hard wired to VCC or GND. The APD3212A/NCP3218A switches between single phase and multi-phase operation with PSI and DPRSLP to optimize power conversion efficiency. Table 1 summarizes PH0 and PH1.
Table 1. PHASE NUMBER CONFIGURATION
PH0 0 1 0 1 PH1 0 0 1 1 Number of Phases Configured 1 1 (GPU Mode) 2 3
The number of phases can be static (see the Number of Phases section) or dynamically controlled by system signals to optimize the power conversion efficiency with heavy and light loads. If APD3212A/NCP3218A is configured for mulit-phase configuration, during a VID transient or with a heavy load condition (indicated by DPRSLP being low and PSI being high), the APD3212A/NCP3218A runs in multi-phase, interleaved PWM mode to achieve minimal VCORE output voltage ripple and the best transient performance possible. If the load becomes light (indicated by PSI being low or DPRSLP being high), APD3212A/NCP3218A switches to single-phase mode to maximize the power conversion efficiency. In addition to changing the number of phases, the APD3212A/NCP3218A is also capable of dynamically changing the control method. In dual-phase operation, the APD3212A/NCP3218A runs in PWM mode, where the switching frequency is controlled by the master clock. In single-phase operation (commanded by the DPRSLP high state), the APD3212A/NCP3218A runs in RPM mode, where the switching frequency is controlled by the ripple voltage appearing on the COMP pin. In RPM mode, the DRVH1 pin is driven high each time the COMP pin voltage rises to a voltage limit set by the VID voltage and an external resistor connected between the RPM pin and GND. In RPM mode, the APD3212A/NCP3218A turns off the low-side (synchronous rectifier) MOSFET when the inductor current drops to 0. Turning off the low-side MOSFETs at the zero current crossing prevents reversed inductor current build up and breaks synchronous operation of high- and low-side switches. Due to the asynchronous operation, the switching frequency becomes slower as the load current decreases, resulting in good power conversion efficiency with very light loads. Table 2 summarizes how the APD3212A/NCP3218A dynamically changes the number of active phases and transitions the operation mode based on system signals and operating conditions.
GPU Mode
In mulit-phase configuration, the timing relationship between the phases is determined by internal circuitry that
The APD3212A/NCP3218A can be used to power IMVP-6.5 GMCH. To configure the APD3212A/NCP3218A in GPU, connect PH1 to VCC and connect PH0 to GND. In GPU mode, the APD3212A/NCP3218A operates in single phase only. In GPU mode, the boot voltage is disabled. During startup, the output voltage ramps up to the programmed VID voltage. There is no other difference between GPU mode and normal CPU mode.
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Table 2. PHASE NUMBER AND OPERATION MODES (Note 1)
VID Transition (Note 2) Yes No No No No No No. of Phases Selected by the User N [3,2 or 1] N [3,2 or 1] * N [3,2 or 1] * * No. of Phases in Operation N N 1 N 1 1 Operation Modes (Note 3) PWM, CCM only PWM, CCM only PWM, CCM only PWM, CCM only RPM, automatic CCM/DCM PWM, CCM only
PSI No. * 1 0 0 * *
DPRSLP * 0 0 0 1 1
Current Limit * * No Yes No Yes
1. * = Don't Care. 2. VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time. 3. CCM stands for continuous current mode, and DCM stands for discontinuous current mode.
VRMP IR = AR x IRAMP
FLIP-FLOP S RD Q BST1 GATE DRIVER BST DRVH DRVH1 IN SW SW1 DCM DRVL DRVL1 SWFB1 R1 BST2 GATE DRIVER BST DRVH DRVH2 IN SW SW2 DCM DRVL DRVL2 SWFB2 CSREF - + LLINE CSCOMP CSSUM RCS RPH RPH VCC RI L VCC RI
CR 1V 400 ns Q Q RD R2 FLIP-FLOP S Q
L LOAD
100 W
30 mV
R2
1V
R1
VDC + - + VCS + COMP FB FBRTN
100 W
RA CFB
CA
CB RFB
CCS
Figure 17. Single-Phase RPM Mode Operation
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ADP3212A, NCP3218A
IR = AR x IRAMP Clock Oscillator CR + - Gate Driver BST1 BST Flip-Flop DRVH1 DRVH IN SQ SW SW1 RD DRVL DRVL1 VCC RL L
AD
SWFB1 0.2 V Gate Driver BST2 BST DRVH2 DRVH IN SW SW2 DRVL DRVL2
100 W
IR = AR x IRAMP Clock Oscillator CR + - Flip-Flop SQ RD
AD
IR = AR x IRAMP Clock Oscillator CR + - Flip-Flop S RD Q PWM3
VCC + COMP RA CFB - + RAMP FB S + FBRTN
+
CSCOMP LLINE
CA CB
RB
Figure 18. 3-Phase PWM Mode Operation
Setting Switch Frequency
Master Clock Frequency in PWM Mode
When the APD3212A/NCP3218A runs in PWM, the clock frequency is set by an external resistor connected from the RT pin to GND. The frequency is constant at a given VID code but varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage maintains constant VCORE ripple and improves power conversion efficiency at lower VID voltages. Figure 7 shows the relationship
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- +
+ -
AD
+ - + -
VCC RL L
SWFB2 0.2 V
100 W Gate Driver BST DRVH IN SW DRVL VCC RL L LOAD
SWFB3 0.2 V + _ DAC _ S CSREF CSSUM
100 W
RPH RPH
RCS CCS
RPH
between clock frequency and VID voltage, parameterized by RT resistance. To determine the switching frequency per phase, divide the clock by the number of phases in use.
Switching Frequency in RPM Mode; Single-Phase Operation
In single-phase RPM mode, the switching frequency is controlled by the ripple voltage on the COMP pin, rather than by the master clock. Each time the COMP pin voltage
ADP3212A, NCP3218A
exceeds the RPM pin voltage threshold level determined by the VID voltage and the external resistor RPM resistor, an internal ramp signal is started and DRVH1 is driven high. The slew rate of the internal ramp is programmed by the current entering the RAMP pin. One-third of the RAMP current charges an internal ramp capacitor (5 pF typical) and creates a ramp. When the internal ramp signal intercepts the COMP voltage, the DRVH1 pin is reset low.
Differential Sensing of Output Voltage
The APD3212A/NCP3218A combines differential sensing with a high accuracy VID DAC, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the Intel IMVP-6.5 specification. In steady-state mode, the combination of the VID DAC and error amplifier maintain the output voltage for a worst-case scenario within 8 mV of the full operating output voltage and temperature range. The CPU core output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the positive regulation point; the VCC remote sensing pin of the microprocessor. FBRTN should be connected directly to the negative remote sensing point; the VSS sensing point of the CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN and have a maximum current of 200 mA for guaranteed accurate remote sensing.
Output Current Sensing
An additional resistor divider connected between the CSCOMP and CSREF pins with the midpoint connected to the LLINE pin can be used to set the load line required by the microprocessor specification. The current information to set the load line is then given as the voltage difference between the LLINE and CSREF pins. This configuration allows the load line slope to be set independent from the current limit threshold. If the current limit threshold and load line do not have to be set independently, the resistor divider between the CSCOMP and CSREF pins can be omitted and the CSCOMP pin can be connected directly to LLINE. To disable voltage positioning entirely (that is, to set no load line), LLINE should be tied to CSREF. To provide the best accuracy for current sensing, the CSA has a low offset input voltage and the sensing gain is set by an external resistor ratio.
Active Impedance Control Mode
The APD3212A/NCP3218A includes a dedicated Current Sense Amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current and for over current detection. Sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low-side MOSFET. The current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by: * Output inductor ESR sensing without the use of a thermistor for the lowest cost. * Output inductor ESR sensing with the use of a thermistor that tracks inductor temperature to improve accuracy. * Discrete resistor sensing for the highest accuracy. At the positive input of the CSA, the CSREF pin is connected to the output voltage. At the negative input (that is, the CSSUM pin of the CSA), signals from the sensing element (in the case of inductor DCR sensing, signals from the switch node side of the output inductors) are summed together by series summing resistors. The feedback resistor between the CSCOMP and CSSUM pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between the CSCOMP and CSREF pins. This signal is used internally as a differential input for the current limit comparator.
To control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between LLINE and CSREF, can be scaled to be equal to the required droop voltage. This droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. This value is used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage, and the resulting voltage is used as the voltage positioning set point. The arrangement results in an enhanced feed forward response.
Current Control Mode and Thermal Balance
The APD3212A/NCP3218A has individual inputs for monitoring the current of each phase. The phase current information is combined with an internal ramp to create a current-balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. The current balance information is independent from the total inductor current information used for voltage positioning described in the Active Impedance Control Mode section. The magnitude of the internal ramp can be set so that the transient response of the system is optimal. The APD3212A/NCP3218A monitors the supply voltage to achieve feed forward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMP pin determines the slope of the internal PWM ramp. More detail about programming the ramp is provided in the Application Information section. External resistors are placed in series with the SWFB1, SWFB2, and SWFB3 pins to create an intentional current imbalance. Such a condition can exist when one phase has better cooling and supports higher currents the other phases. Resistors RSWSB1, RSWFB2, and RSWFB3 (see Figure 25) can be used to adjust thermal balance. It is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout.
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To increase the current in any given phase, users should make RSWFB for that phase larger (that is, RSWFB = 100 W for the hottest phase and do not change it during balance optimization). Increasing RSWFB to 150 W makes a substantial increase in phase current. Increase each RSWFB value by small amounts to achieve thermal balance starting with the coolest phase. If adjusting current balance between phases is not needed, RSWFB should be 100 W for all phases.
VDC ADP3212 SWFB1 RSWFB1 33 VDC RSWFB2 28 VDC RSWFB3 24 Phase 3 Inductor Phase 2 Inductor Phase 1 Inductor
PWRGD range is monitored. To prevent a false alarm, the power-good circuit is masked during various system transitions, including a VID change and entrance into or exit out of deeper sleep. The duration of the PWRGD mask is set to approximately 130 ms by an internal timer. If the voltage drop is greater than 200 mV during deeper sleep entry or slow deeper sleep exit, the duration of PWRGD masking is extended by the internal logic circuit.
Powerup Sequence and Soft-Start
SWFB2
The power-on ramp-up time of the output voltage is set internally. The APD3212A/NCP3218A steps sequentially through each VID code until it reaches the boot voltage. The powerup sequence, including the soft-start is illustrated in Figure 20. After EN is asserted high, the soft-start sequence starts. The core voltage ramps up linearly to the boot voltage. The APD3212A/NCP3218A regulates at the boot voltage for approximately 90 ms. After the boot time is over, CLKEN is asserted low. Before CLKEN is asserted low, the VID pins are ignored. 9 ms after CLKEN is asserted low, PWRGD is asserted high.
VCC = 5 V EN VBOOT = 1.1 V VCORE tBOOT CLKEN tCPU_PWRGD PWRGD
SWFB3
Figure 19. Current Balance Resistors Voltage Control Mode
A high-gain bandwidth error amplifier is used for the voltage mode control loop. The non-inverting input voltage is set via the 7-bit VID DAC. The VID codes are listed in Table 3. The non-inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage of the internal PWM ramps. At the negative input, the FB pin is tied to the output sense location using RB, a resistor for sensing and controlling the output voltage at the remote sensing point. The main loop compensation is incorporated in the feedback network connected between the FB and COMP pins.
Power-Good Monitoring
Figure 20. Powerup Sequence of APD3212A/NCP3218A Current Limit
The APD3212A/NCP3218A compares the differential output of a current sense amplifier to a programmable current limit set point to provide the current limiting function. The current limit threshold is set by the user with a resistor connected from the ILIM pin to CSCOMP.
Changing VID On-The-Fly (OTF)
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output that can be pulled up through an external resistor to a voltage rail; not necessarily the same VCC voltage rail that is running the controller. A logic high level indicates that the output voltage is within the voltage limits defined by a range around the VID voltage setting. PWRGD goes low when the output voltage is outside of this range. Following the IMVP-6.5 specification, the PWRGD range is defined to be 300 mV less than and 200 mV greater than the actual VID DAC output voltage. For any DAC voltage less than 300 mV, only the upper limit of the
The APD3212A/NCP3218A is designed to track dynamically changing VID code. As a consequence, the CPU VCC voltage can change without the need to reset the controller or the CPU. This concept is commonly referred to as VID OTF transient. A VID OTF can occur with either light or heavy load conditions. The processor alerts the controller that a VID change is occurring by changing the VID inputs in LSB incremental steps from the start code to the finish code. The change can be either upwards or downwards steps.
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When a VID input changes, the APD3212A/NCP3218A detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7-bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. As listed in Table 3, during a VID transient, the APD3212A/NCP3218A forces PWM mode regardless of the state of the system input signals. For example, this means that if the chip is configured as a dual-phase controller but is running in single-phase mode due to a light load condition, a current overload event causes the chip to switch to dual-phase mode to share the excessive load until the delayed current limit latchoff cycle terminates. In user-set single-phase mode, the APD3212A/NCP3218A usually runs in RPM mode. When a VID transition occurs, however, the APD3212A/NCP3218A switches to dual-phase PWM mode.
Light Load RPM DCM Operation
In single-phase normal mode, DPRSLP is pulled low and the APD3208 operates in Continuous Conduction Mode (CCM) over the entire load range. The upper and lower MOSFETs run synchronously and in complementary phase. See Figure 21 for the typical waveforms of the APD3212A/NCP3218A running in CCM with a 7 A load current.
4 OUTPUT VOLTAGE 20 mV/DIV INDUCTOR CURRENT 5 A/DIV 2 SWITCH NODE 5 V/DIV 3 1 LOW-SIDE GATE DRIVE 5 V/DIV
In DCM with a light load, the APD3212A/NCP3218A monitors the switch node voltage to determine when to turn off the low-side FET. Figure 27 shows a typical waveform in DCM with a 1 A load current. Between t1 and t2, the inductor current ramps down. The current flows through the source drain of the low-side FET and creates a voltage drop across the FET with a slightly negative switch node. As the inductor current ramps down to 0 A, the switch voltage approaches 0 V, as seen just before t2. When the switch voltage is approximately -6 mV, the low-side FET is turned off. Figure 26 shows a small, dampened ringing at t2. This is caused by the LC created from capacitance on the switch node, including the CDS of the FETs and the output inductor. This ringing is normal. The APD3212A/NCP3218A automatically goes into DCM with a light load. Figure 27 shows the typical DCM waveform of the APD3212A/NCP3218A. As the load increases, the APD3212A/NCP3218A enters into CCM. In DCM, frequency decreases with load current. Figure 28 shows switching frequency vs. load current for a typical design. In DCM, switching frequency is a function of the inductor, load current, input voltage, and output voltage.
Q1 DRVH Q2 DRVL SWITCH NODE L C LOAD OUTPUT VOLTAGE
INPUT VOLTAGE
Figure 22. Buck Topology
ON L OFF C LOAD
Figure 23. Buck Topology Inductor Current During t0 and t1
400 ns/DIV OFF ON L C LOAD
Figure 21. Single-Phase Waveforms in CCM
If DPRSLP is pulled high, the APD3212A/NCP3218A operates in RPM mode. If the load condition is light, the chip enters Discontinuous Conduction Mode (DCM). Figure 22 shows a typical single-phase buck with one upper FET, one lower FET, an output inductor, an output capacitor, and a load resistor. Figure 23 shows the path of the inductor current with the upper FET on and the lower FET off. In Figure 24, the high-side FET is off and the low-side FET is on. In CCM, if one FET is on, its complementary FET must be off; however, in DCM, both high- and low-side FETs are off and no current flows into the inductor (see Figure 25). Figure 26 shows the inductor current and switch node voltage in DCM.
Figure 24. Buck Topology Inductor Current During t1 and t2
OFF OFF
L C LOAD
Figure 25. Buck Topology Inductor Current During t2 and t3
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ADP3212A, NCP3218A
Output Crowbar
Inductor Current
Switch Node Voltage
t0 t1
t2
t3 t4
Figure 26. Inductor Current and Switch Node in DCM
To prevent the CPU and other external components from damage due to overvoltage, the APD3212A/NCP3218A turns off the DRVH1 and DRVH2 outputs and turns on the DRVL1 and DRVL2 outputs when the output voltage exceeds the OVP threshold (1.55 V typical). Turning on the low-side MOSFETs forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. If the output overvoltage is due to a drain-source short of the high-side MOSFET, turning on the low-side MOSFET results in a crowbar across the input voltage rail. The crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the microprocessor from destruction. When the OVP feature is triggered, the APD3212A/NCP3218A is latched off. The latchoff function can be reset by removing and reapplying VCC to the APD3212A/NCP3218A or by briefly pulling the EN pin low. Pulling TTSNS to less than 1.0 V disables the overvoltage protection function. In this configuration, VRTT should be tied to ground.
Reverse Voltage Protection
4
OUTPUT VOLTAGE 20 mV/DIV SWITCH NODE 5 V/DIV
2
INDUCTOR CURRENT 5 A/DIV
3
1
LOW-SIDE GATE DRIVE 5 V/DIV 2 s/DIV
Figure 27. Single-Phase Waveforms in DCM with 1 A Load Current
400 350 FREQUENCY (kHz) 300 250 19 V INPUT 200 150 100 50 0 0 2 4 6 8 10 LOAD CURRENT (A) 12 14 9 V INPUT
Very large reverse current in inductors can cause negative VCORE voltage, which is harmful to the CPU and other output components. The APD3212A/NCP3218A provides a Reverse Voltage Protection (RVP) function without additional system cost. The VCORE voltage is monitored through the CSREF pin. When the CSREF pin voltage drops to less than -300 mV, the APD3212A/NCP3218A triggers the RVP function by disabling all PWM outputs and driving DRVL1 and DRVL2 low, thus turning off all MOSFETs. The reverse inductor currents can be quickly reset to 0 by discharging the built-up energy in the inductor into the input dc voltage source via the forward-biased body diode of the high-side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns to greater than -100 mV. Sometimes the crowbar feature inadvertently causes output reverse voltage because turning on the low-side MOSFETs results in a very large reverse inductor current. To prevent damage to the CPU caused from negative voltage, the APD3212A/NCP3218A maintains its RVP monitoring function even after OVP latchoff. During OVP latchoff, if the CSREF pin voltage drops to less than -300 mV, the low-side MOSFETs is turned off. DRVL outputs are allowed to turn back on when the CSREF voltage recovers to greater than -100 mV.
Output Enable and UVLO
Figure 28. Single-Phase CCM/DCM Frequency vs. Load Current
For the APD3212A/NCP3218A to begin switching, the VCC supply voltage to the controller must be greater than the VCCOK threshold and the EN pin must be driven high. If the VCC voltage is less than the VCCUVLO threshold or the EN pin is a logic low, the APD3212A/NCP3218A shuts off. In shutdown mode, the controller holds the PWM outputs low, shorts the capacitors of the SS and PGDELAY pins to ground, and drives the DRVH and DRVL outputs low.
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ADP3212A, NCP3218A
The user must adhere to proper power-supply sequencing during startup and shutdown of the APD3212A/ NCP3218A. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off.
Thermal Throttling Control
The APD3212A/NCP3218A includes a thermal monitoring circuit to detect whether the temperature of the VR has exceeded a user-defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSNS pin. An internal comparator circuit compares the TTSNS voltage to half the VCC threshold and outputs a
Table 3. VID CODE TABLE
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
logic level signal at the VRTT output when the temperature trips the user-set alarm threshold. The VRTT output is designed to drive an external transistor that in turn provides the high current, open-drain VRTT signal required by the IMVP-6.5 specification. The internal VRTT comparator has a hysteresis of approximately 100 mV to prevent high frequency oscillation of VRTT when the temperature approaches the set alarm point.
Output Current Monitor
The APD3212A/NCP3218A has an output current monitor. The IMON pin sources a current proportional to the inductor current. A resistor from IMON pin to FBRTN sets the gain. A 0.1 mF is added in parallel with RMON to filter the inductor ripple. The IMON pin is clamped to prevent it from going above 1.15 V.
VID1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Output (V) 1.5000 V 1.5000 V 1.4875 V 1.4750 V 1.4625 V 1.4500 V 1.4375 V 1.4250 V 1.4125 V 1.4000 V 1.3875 V 1.3750 V 1.3625 V 1.3500 V 1.3375 V 1.3250 V 1.3125 V 1.3000 V 1.2875 V 1.2750 V 1.2625 V 1.2500 V 1.2375 V 1.2250 V 1.2125 V 1.2000 V 1.1875 V 1.1750 V 1.1625 V 1.1500 V 1.1375 V 1.1250 V 1.1125 V
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ADP3212A, NCP3218A
Table 3. VID CODE TABLE (continued)
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output (V) 1.1000 V 1.0875 V 1.0750 V 1.0625 V 1.0500 V 1.0375 V 1.0250 V 1.0125 V 1.0000 V 0.9875 V 0.9750 V 0.9625 V 0.9500 V 0.9375 V 0.9250 V 0.9125 V 0.9000 V 0.8875 V 0.8750 V 0.8625 V 0.8500 V 0.8375 V 0.8250 V 0.8125 V 0.8000 V 0.7875 V 0.7750 V 0.7625 V 0.7500 V 0.7375 V 0.7250 V 0.7125 V 0.7000 V 0.6875 V 0.6750 V 0.6625 V 0.6500 V 0.6375 V 0.6250 V 0.6125 V 0.6000 V 0.5875 V 0.5750 V 0.5625 V 0.5500 V 0.5375 V 0.5250 V 0.5125 V 0.5000 V
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ADP3212A, NCP3218A
Table 3. VID CODE TABLE (continued)
VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output (V) 0.4875 V 0.4750 V 0.4625 V 0.4500 V 0.4375 V 0.4250 V 0.4125 V 0.4000 V 0.3875 V 0.3750 V 0.3625 V 0.3500 V 0.3375 V 0.3250 V 0.3125 V 0.3000 V 0.2875 V 0.2750 V 0.2625 V 0.2500 V 0.2375 V 0.2250 V 0.2125 V 0.2000 V 0.1875 V 0.1750 V 0.1625 V 0.1500 V 0.1375 V 0.1250 V 0.1125 V 0.1000 V 0.0875 V 0.0750 V 0.0625 V 0.0500 V 0.0375 V 0.0250 V 0.0125 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V
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ADP3212A, NCP3218A
Thermistor R4 should be placed close to the hot spot of the board. J3 COMP J2 TRDET V5S
2 1 1 2 2
R45 1 3k V3.3S
2
1
2
R1
C6 330p 2 1 1.65 k 390 pF 39.2 k R12 2 1 C72 1 R13 2
1
1
1
R11 0
R68
1
C104
1
860 pF
69.8 k R67 1 2 4.99 k VRTT
2
1
C5 1n
2
3k1 R46
R4 100 k Therm.. 5%
7.32 k
CLKEN#
1
PWRGD
J22
2
VSSSense VSSSense SHORTPIN
2
VCCSense 100 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 JP11 VCCSense
1
DNP
R73 2
PWRGD
1
J23
2
C1
1
1
1
1
1
100 R50 2 VCC(core) RTN
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF 10 mF
3 2 1 4 5 6 7 8 3 2 1 2 2 1 1
R10
2
TTSense
12 11
2
12p C8
10n X7R
1
1 0
TTSense
R60 2
1
IMON 7.50 k
J6 VSS_S C651 Up to 32 pieces of MLCC, X5R, 0805, 6.3 V.
1 1 1
J5 VCC_S VDC R18 1 2 1n CSREF J7 CON2
12 12 2 2
R74
2 2 2
VR_ON
0.1 m C4
1
J24
2
1
10
R27
9
8
7
6
5
4
3
2
1
1
TRDET
GND
TTSNS
VRTT
COMP
FB
FBRTN
CLKEN
IMON
PWRGD
EN
VARFREQ
80.6 k R15 1 280 k R16 1 402 k R17 1 280 k
U1
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20
IREF RPM RT
VID0 VID1 VID2 VID3 VID4 VID5 VID6
PSI
VID0 VID1 VID2 VID3 VID4 VID5 VID6 PSI DPRSLPVR
2 2
2
1
R20 1 DNP
1
2
1n
0
2
VCC(core)
2
1 2
C14
C11
RAMP LLINE CSREF CSSUM CSCOMP ILIM
OD3
R19
0
DNP1 R70 DNP 1 R72
2
0 R69 0
1
ADP3212A LFCSP48
V5S
1
2
C12
2
2
R14
1 21 22 23
R71
1
150p C13
2
4.53 k R26 R25 R24 R52 R63 DNP R21 2
1
DPRSLP PH0 PH1 VCC BST1 SWFB2 DRVH2 SWFB1 DRVH1 DRVL2 DRVL1 PGND PVCC SW2 SW1
1.5n 165 k R22
2
PWM3 SWFB3 BST2
R51
24 1
1 2
1 2
1
1
1
1
2
C3 1
R66 2
2
0
115 k
115 k
115 k
DNP
DNP
2
2
2
2
73.2 k
1
1 mF/16 V X7R(0805)
1
R8 10 V5S
25
26
27
28 1
29
30
31
32
33 1
34
35
36
R23
R61
R62
2
SW3
PH3_CS+ V5S
5 4 3 2 1
0
0
Place R23 close to output inductor of phase 1. 220kTHERMISTOR 5% VCC DRVL
2
2
4.7 mF
1 2
C15
1 1
R33 2
2
2
R32 1 0
2 1
C22 0
0.47 m
0.47 m
C16
CROWBAR GND
7
DRVLSD
IN
SD
U13 ADP3611
4 pieces of Panasonic SP CAP (SD) or Sanyo POSCAP.
2 2
4.7 mF/ 16 V X5R (1206) C14
2 1
DRVH
4 5 6 7 8 3 2 1
5 6 7 8
4 3 2 1 3 2 1
4
BST
5 6 7 8 3 2 1
SW
4
10
Q22 NTMFS4821N
6
8
Q20 NTMFS4821N C79 R57
9 4
Q9 NTMFS4846N
Q4 NTMFS4846N
5 6 7 8
Q2 NTMFS4821N
R42 1 0 C78
1
Q7 NTMFS4821N Q8 NTMFS4821N C102
1
2
C101
1
0.47 m
5 6 7 8
1n C23
1
2
1
R56 DNP
1
21 B
C29
2
2
C28
1 A
2
R55 1 DNP
1
1n
2 1
DNP
2
DNP
2
C17 10 mF
2 1
2
10 mF C24
1
D8
DNP
D5
DNP
C18 10 mF
2 1
2
1 C
2
1
10 mF C25 C103
2 1 1
C19 10 mF
2 1
2
DNP D9
DNP
1 1
330 mF C66 2 330 mF C67 2 1
2
DNP
2
1n C21
1
10 mF C26
1
C20 10 mF
1
VDC
1
1
SW2
SW1
J8
J9
1
2
10 mF VDC
L2
NEC Tokin MPCG10LR45 0.45 mH/ESR = 1.1 mW
1
0.45 mH/ESR = 1.1 mW
PH3_CS+
L3
2
2
10 mF C30
1
R54 10
2
2
R53 10
L1
2 1
NEC Tokin MPCG10LR45 0.45 mH/ESR = 1.1 mW
SW3
J26
SW3
2
1
DNP C68 1 DNP C69
2
10 mF C31
1
Note 2
Note 2
PH1 VCORE cut
PH2 VCORE cut
PH3 VCORE cut
(Optional)
10 mF C32
2 1
(Optional)
1
RS1 DNP
RS2 DNP
1
1
1
CSREF
CSREF
JP2
JP3
RS3 DNP
R64 10
1
1
1
Note 2
VDC
JP4
2
2
2
2
2
10 mF
330 mF C70 2 330 mF
1
2
2
1
2
2
2
2
1
R31 DNP
R30 DNP IMVP-6.5 solution for Penryn processor: 3-phase/55-65 A
R65 DNP
Note 3
VCORE
CSREF
VCORE
Figure 29. Typical Dual-Phase Application Circuit
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ADP3212A, NCP3218A
Application Information
The design parameters for a typical IMVP-6.5-compliant CPU core VR application are as follows: * Maximum input voltage (VINMAX) = 19 V * Minimum input voltage (VINMIN) = 8.0 V * Output voltage by VID setting (VVID) = 1.05 V * Maximum output current (IO) = 52 A * Droop resistance (RO) = 1.9 mW * Nominal output voltage at 40 A load (VOFL) = 0.9512 V * Static output voltage drop from no load to full load (DV) = VONL - VOFL = 1.05 V - 0.9512 V = 98 mV * Maximum output current step (DIO) = 52 A * Number of phases (n) = 2 * Switching frequency per phase (SW) = 300 kHz * Duty cycle at maximum input voltage (DMAX) = 0.13 V * Duty cycle at minimum input voltage (DMIN) = 0.055 V
Setting the Clock Frequency for PWM
To save power with light loads, lower switching frequency is usually preferred during RPM operation. However, the VCORE ripple specification of IMVP-6.5 sets a limitation for the lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM can be equal to, greater than, or less than its counterpart in PWM. A resistor from RPM to GND sets the pseudo constant frequency as following:
R RPM + RT V VID ) 1.0 V 2 A R (1 * D) V VID * 0.5 kW R R C R f SW
(eq. 3)
where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude.
Soft-Start and Current Limit Latchoff Delay Times Inductor Selection
In PWM operation, the APD3212A/NCP3218A uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. For a dual-phase design, a clock frequency of 600 kHz sets the switching frequency to 300 kHz per phase. This selection represents the trade-off between the switching losses and the minimum sizes of the output filter components. To achieve a 600 kHz oscillator frequency at a VID voltage of 1.2 V, RT must be 181 kW. Alternatively, the value for RT can be calculated by using the following equation:
RT + 2 V VID ) 1.0 V * 16 kW n f SW 9 pF
(eq. 1)
where: 9 pF and 16 kW are internal IC component values. VVID is the VID voltage in volts. n is the number of phases. SW is the switching frequency in hertz for each phase. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. When VARFREQ pin is connected to ground, the switching frequency does not change with VID. The value for RT can be calculated by using the following equation.
RT + n 2 1.0 V f SW 9 pF * 16 kW
(eq. 2)
The choice of inductance determines the ripple current of the inductor. Less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs. However, this allows the use of smaller-size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. For a multi-phase converter, the practical value for peak-to-peak inductor ripple current is less than 50% of the maximum dc current of that inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current. Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage.
IR + Lw V VID (1 * D MIN) f SW L RO f SW 1 * (n D MIN) V RIPPLE
(eq. 4)
V VID
(eq. 5)
Solving Equation 5 for a 16 mV peak-to-peak output ripple voltage yields:
Lw 1.05 V 1.9 mW 300 kHz (1 * 2 16 mV 0.055) + 528 nH
Setting the Switching Frequency for RPM Operation of Phase 1
During the RPM operation of Phase 1, the APD3212A/NCP3218A runs in pseudoconstant frequency if the load current is high enough for continuous current mode. While in DCM, the switching frequency is reduced with the load current in a linear manner.
If the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 490 nH inductor is a good choice for a starting point, and it provides a calculated ripple current of 9.0 A. The inductor should not saturate at the peak current of 24.5 A, and it should be able to handle the sum of the power dissipation caused by the
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ADP3212A, NCP3218A
winding's average current (20 A) plus the ac core loss. In this example, 330 nH is used. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. Too large of a DCR causes excessive power losses, whereas too small of a value leads to increased measurement error. For this example, an inductor with a DCR of 0.8 mW is used.
Selecting a Standard Inductor
and CCS (filters). The output resistance of the regulator is set by the following equations:
RO + R CS R PH(x) R SENSE R CS
(eq. 6)
C CS +
L R SENSE
(eq. 7)
After the inductance and DCR are known, select a standard inductor that best meets the overall design goals. It is also important to specify the inductance and DCR tolerance to maintain the accuracy of the system. Using 20% tolerance for the inductance and 15% for the DCR at room temperature are reasonable values that most manufacturers can meet.
Power Inductor Manufacturers
where RSENSE is the DCR of the output inductors. Either RCS or RPH(x) can be chosen for added flexibility. Due to the current drive ability of the CSCOMP pin, the RCS resistance should be greater than 100 kW. For example, initially select RCS to be equal to 200 kW, and then use Equation 7 to solve for CCS:
C CS + 330 nH + 2.1 nF 0.8 mW 200 kW
The following companies provide surface-mount power inductors optimized for high power applications upon request: * Vishay Dale Electronics, Inc. (605) 665-9301 * Panasonic (714) 373-7334 * Sumida Electric Company (847) 545-6700 * NEC Tokin Corporation (510) 324-4110
Output Droop Resistance
If CCS is not a standard capacitance, RCS can be tuned. For example, if the optimal CCS capacitance is 1.5 nF, adjust RCS to 280 kW. For best accuracy, CCS should be a 5% NPO capacitor. In this example, a 220 kW is used for RCS to achieve optimal results. Next, solve for RPH(x) by rearranging Equation 6 as follows:
R PH(x) w 0.8 mW 2.1 mW 220 kW + 83.8 kW
The standard 1% resistor for RPH(x) is 86.6 kW.
Inductor DCR Temperature Correction
The design requires that the regulator output voltage measured at the CPU pins decreases when the output current increases. The specified voltage drop corresponds to the droop resistance (RO). The output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. The summing is implemented by the CS amplifier that is configured with resistor RPH(x) (summer) and resistors RCS
Place as close as possible to nearest inductor ADP3212 CSCOMP 19 RTH
If the DCR of the inductor is used as a sense element and copper wire is the source of the DCR, the temperature changes associated with the inductor's winding must be compensated for. Fortunately, copper has a well-known Temperature Coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, series resistors RCS1 and RCS2 (see Figure 30) are needed to linearize the NTC and produce the desired temperature coefficient tracking.
To Switch Nodes RPH1 RPH2 RPH3 To VOUT Sense
RCS1 RCS2 CCS1
CCS2 CSSUM 18 - + CSREF 17
Keep This Path As Short As Possible And Well Away From Switch Node Lines
Figure 30. Temperature-Compensation Circuit Values
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ADP3212A, NCP3218A
The following procedure and expressions yield values for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value. 1. Select an NTC to be used based on its type and value. Because the value needed is not yet determined, start with a thermistor with a value close to RCS and an NTC with an initial tolerance of better than 5%. 2. Find the relative resistance value of the NTC at two temperatures. The appropriate temperatures will depend on the type of NTC, but 50C and 90C have been shown to work well for most types of NTCs. The resistance values are called A (A is RTH(50C)/RTH(25C)) and B (B is RTH(90C)/RTH(25C)). Note that the relative value of the NTC is always 1 at 25C. 3. Find the relative value of RCS required for each of the two temperatures. The relative value of RCS is based on the percentage of change needed, which is initially assumed to be 0.39%/C in this example. The relative values are called r1 (r1 is 1/(1+ TC x (T1 - 25))) and r2 (r2 is 1/(1 + TC x (T2 - 25))), where TC is 0.0039, T1 is 50C, and T2 is 90C. 4. Compute the relative values for rCS1, rCS2, and rTH by using the following equations:
r CS2 +
(A-B) r 1 r 2 * A (1-B) r 2 ) B (1-A) r 1 A (1 * B) r 1 * B (1 * A) r 2 * (A * B)
6. Calculate values for RCS1 and RCS2 by using the following equations:
R CS1 + R CS R CS2 + R CS k r CS1 r CS2) (1 * k) ) (k
(eq. 10)
For example, if a thermistor value of 100 kW is selected in Step 1, an available 0603-size thermistor with a value close to RCS is the Vishay NTHS0603N04 NTC thermistor, which has resistance values of A = 0.3359 and B = 0.0771. Using the equations in Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH yields 241 kW, so a thermistor of 220 kW would be a reasonable selection, making k equal to 0.913. Finally, RCS1 and RCS2 are found to be 72.1 kW and 166 kW. Choosing the closest 1% resistor for RCS2 yields 165 kW. To correct for this approximation, 73.3 kW is used for RCS1. The required output decoupling for processors and platforms is typically recommended by Intel. For systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. Select the number of ceramics and determine the total ceramic capacitance (CZ). This is based on the number and type of capacitors used. Keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805-size pieces inside the socket. Additional ceramic capacitors can be placed along the outer edge of the socket. A combined ceramic capacitor value of 200 mF to 300 mF is recommended and is usually composed of multiple 10 mF or 22 mF capacitors. Ensure that the total amount of bulk capacitance (CX) is within its limits. The upper limit is dependent on the VID OTF output voltage stepping (voltage step, VV, in time, tV, with error of VERR); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, DIO. The current version of the IMVP-6.5 specification allows a maximum VCORE overshoot (VOSMAX) of 10 mV more than the VID voltage for a step-off load current.
L n DI O V VID
2
COUT Selection
r CS1 +
(1 * A) 1 A * 1*r CS2 r1*r CS2
(eq. 8)
r TH +
1 1 *1 1*rCS2 rCS1
5. Calculate RTH = rTH x RCS, and then select a thermistor of the closest value available. In addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one:
k+ R TH(ACTUAL) R TH(CALCULATED)
(eq. 9)
C X(MIN) w
V R O ) OSMAX DIO V 1 ) t v VID VV V ERR VV n
* CZ
(eq. 11)
C X(MAX) v
n
k2
L
RO 2
VV V VID where k + - ln
k L
RO
* 1 * CZ
(eq. 12)
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ADP3212A, NCP3218A
To meet the conditions of these expressions and the transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is greater than CX(MAX), the system does not meet the VID OTF and/or the deeper sleep exit specifications and may require less inductance or more phases. In addition, the switching frequency may have to be increased to maintain the output ripple. For example, if 30 pieces of 10 mF, 0805-size MLC capacitors (CZ = 300 mF) are used, the fastest VID voltage change is when the device exits deeper sleep, during which the VCORE change is 220 mV in 22 ms with a setting error of 10 mV. If k = 3.1, solving for the bulk capacitance yields
C X(MIN) w 330 nH 2 C X(MAX) v 27.9 A 1.4375 V
the APD3212A/NCP3218A, currents are balanced between phases; the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO):
P SF + (1-D) IO n SF
2
)1 12
n
n SF
IR
2
R DS(SF)
(eq. 14)
10 mV 2.1 mW ) 27.9 A
* 300 mF + 1.0 mF
where: D is the duty cycle and is approximately the output voltage divided by the input voltage. IR is the inductor peak-to-peak ripple current and is approximately
IR + (1 * D) V OUT L f SW
2
330 nH 220 mV 3.1 2 (2.1 mW) 2 1.4375 V 1.4375V 220 mV 2 3.1 490 nH 2.1mW
2
1) + 21 mF
22ms
-1
-300 mF
Using six 330 mF Panasonic SP capacitors with a typical ESR of 7 mW each yields CX = 1.98 mF and RX = 1.2 mW. Ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using:
LX v CZ RO 2 Q2 2 + 2 nH L X v 300 mF (2.1 mW) 2
(eq. 13)
where: Q is limited to the square root of 2 to ensure a critically damped system. LX is about 150 pH for the six SP capacitors, which is low enough to avoid ringing during a load change. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. For this multimode control technique, an all ceramic capacitor design can be used if the conditions of Equations 11, 12, and 13 are satisfied.
Power MOSFETs
Knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required RDS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOIC compatible MOSFETs, the junction-to- ambient (PCB) thermal impedance is 50C/W. In the worst case, the PCB temperature is 70C to 80C during heavy load operation of the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W at 120C junction temperature. Therefore, for this example (40 A maximum), the RDS(SF) per MOSFET is less than 8.5 mW for two pieces of low-side MOSFETs. This RDS(SF) is also at a junction temperature of about 120C; therefore, the RDS(SF) per MOSFET should be less than 6 mW at room temperature, or 8.5 mW at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction losses and switching losses. Switching loss is related to the time for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET:
P S(MF) + 2 f SW V DC I O n MF RG n MF n C ISS
(eq. 15)
For typical 20 A per phase applications, the N-channel power MOSFETs are selected for two high-side switches and two or three low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the voltage of the gate driver is 5.0 V, logic-level threshold MOSFETs must be used. The maximum output current, IO, determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. In
where: nMF is the total number of main MOSFETs. RG is the total gate resistance. CISS is the input capacitance of the main MOSFET.
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ADP3212A, NCP3218A
The most effective way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation:
P C(MF) + D IO n MF
2
)1 12
n
n MF
IR
2
R DS(MF)
(eq. 16)
where RDS(MF) is the on resistance of the MOSFET. Typically, a user wants the highest speed (low CISS) device for a main MOSFET, but such a device usually has higher on resistance. Therefore, the user must select a device that meets the total power dissipation (about 0.8 W to 1.0 W for an 8-lead SOIC) when combining the switching and conduction losses. For example, an IRF7821 device can be selected as the main MOSFET (four in total; that is, nMF = 4), with approximately CISS = 1010 pF (maximum) and RDS(MF) = 18 mW (maximum at TJ = 120C), and an IR7832 device can be selected as the synchronous MOSFET (four in total; that is, nSF = 4), with RDS(SF) = 6.7 mW (maximum at TJ = 120C). Solving for the power dissipation per MOSFET at IO = 40 A and IR = 9.0 A yields 630 mW for each synchronous MOSFET and 590 mW for each main MOSFET. A third synchronous MOSFET is an option to further increase the conversion efficiency and reduce thermal stress. Finally, consider the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation:
P DRV + 2 f SW n (n MF Q GMF ) n SF Q GSF) ) I CC VCC (eq. 17)
RDS is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 19). For stability and noise immunity, keep the ramp size larger than 0.5 V. Taking this into consideration, the value of RR in this example is selected as 280 kW. The internal ramp voltage magnitude can be calculated as follows:
VR + A R (1 * D) V VID R R C R f SW
(eq. 19)
0.5 (1 * 0.061) 1.150 V VR + + 0.83 V 462 kW 5 pF 280 kHz
The size of the internal ramp can be increased or decreased. If it is increased, stability and transient response improves but thermal balance degrades. Conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. In the denominator of Equation 18, the factor of 3 sets the minimum ramp size that produces an optimal combination of good stability, transient response, and thermal balance.
Current Limit Setpoint
To select the current limit setpoint, the resistor value for RCLIM must be determined. The current limit threshold for the APD3212A/NCP3218A is set with RCLIM. RCLIM can be found using the following equation:
R LIM + I LIM R O 60 mA
(eq. 20)
where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET. The previous equation also shows the standby dissipation (ICC times the VCC) of the driver.
Ramp Resistor Selection
The ramp resistor (RR) is used to set the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use the following expression to determine a starting value:
RR + RR + 3 3 AR L A D R DS CR
where: RLIM is the current limit resistor. RO is the output load line. ILIM is the current limit setpoint. When the APD3212A/NCP3218A is configured for 3 phase operation, the equation above is used to set the current limit. When the APD3212A/NCP3218A switches from 3 phase to 1 phase operation by PSI or DPRSLP signal, the current is single phase is one third of the current limit in 3 phase. When the APD3212A/NCP3218A is configured for 2 phase operation, the equation above is used to set the current limit. When the APD3212A/NCP3218A switches from 2 phase to 1 phase operation by PSI or DPRSLP signal, the current is single phase is one half of the current limit in 2 phase. When the APD3212A/NCP3218A is configured for 1 phase operation, the equation above is used to set the current limit.
Current Monitor
0.5 360 nH + 462 kW 5 5.2 mW 5 pF
(eq. 18)
where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain.
The APD3212A/NCP3218A has output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN sets the gain of the output current monitor. A 0.1 mF is placed in parallel with RMON to filter the inductor current ripple and
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ADP3212A, NCP3218A
high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15 V. The IMON pin current is equal to the RLIM times a fixed gain of 4. RMON can be found using the following equation:
R MON + 1.15 V R LIM 4 R O I FS
(eq. 21) Gain -20 dB/dec
-20 dB/dec
where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale.
Feedback Loop Compensation Design
0 dB fZ1 fP0 fP1 fZ2 Frequency
Figure 32. Poles and Zeros of Voltage Error Amplifier
The following equations give the locations of the poles and zeros shown in Figure 32:
f Z1 + f Z2 + f P0 + f P1 + 2p 2p 2p 2p 1 CA 1 C FB RA R FB R FB CA
(eq. 22) (eq. 23) (eq. 24)
Optimized compensation of the APD3212A/NCP3218A allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. With the multimode feedback structure of the APD3212A/NCP3218A, it is necessary to set the feedback compensation so that the converter's output impedance works in parallel with the output decoupling. In addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 31 shows the Type III amplifier used in the APD3212A/NCP3218A. Figure 32 shows the locations of the two poles and two zeros created by this amplifier.
VOLTAGE ERROR AMPLIFIER REFERENCE VOLTAGE
1 (C A ) C B) CA ) CB RA CB
(eq. 25)
The expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for 12 section):
RE + n 2 L n RO ) AD R DS ) R L V RT ) V VID
(1 * (n D)) V RT C X R O V VID (R O * R ) ) LX RO CX RO * R RX
(eq. 26)
TA + CX
(eq. 27) (eq. 28)
T B + (R X ) R * R O) V RT TC + L* V VID CX
AD RDS 2 f SW RE RO
(eq. 29)
COMP
FB
ADP3212
TD +
RA CB CA CFB OUTPUT VOLTAGE
CX CZ RO 2 (R O * R ) ) C Z
(eq. 30)
RFB
Figure 31. Voltage Error Amplifier
where: R is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.4 mW (assuming an 8-layer motherboard). RDS is the total low-side MOSFET for on resistance per phase. AD is 5. VRT is 1.25 V. LX is 150 pH for the six Panasonic SP capacitors.
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ADP3212A, NCP3218A
The compensation values can be calculated as follows:
CA + RA + CB + n TC CA TB RB TD RA RE RO RB TA
(eq. 31)
C Snubber +
p
1 f Ringing
R Snubber f Switching
(eq. 37) (eq. 38)
P Snubber + C Snubber
V Input 2
(eq. 32)
(eq. 33)
C FB +
(eq. 34)
The standard values for these components are subject to the tuning procedure described in the Tuning Procedure for 12 section. In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude that is one-nth of the maximum output current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum rms current. The maximum rms capacitor current occurs at the lowest input voltage and is given by:
I CRMS + D I CRMS + 0.18 IO 40 A n 1 D 2 *1
(eq. 35)
Where RSnubber is the snubber resistor. CSnubber is the snubber capacitor. fRininging is the frequency of the ringing on the switch node when the high side MOSFET turns on. COSS is the low side MOSFET output capacitance at VInput. This is taken from the low side MOSFET data sheet. Vinput is the input voltage. fSwitching is the switching frequency. PSnubber is the power dissipated in RSnubber.
Selecting Thermal Monitor Components
CIN Selection and Input Current di/dt Reduction
To monitor the temperature of a single-point hot spot, set RTTSET1 equal to the NTC thermistor's resistance at the alarm temperature. For example, if the alarm temperature for VRTT is 100C and a Vishey thermistor (NTHS-0603N011003J) with a resistance of 100 kW at 25C, or 6.8 kW at 100C, is used, the user can set RTTSET1 equal to 6.8 kW (the RTH1 at 100C).
VRTT VCC 5V
1 * 1 + 9.6 A 0.18
R
RTTSET1
where IO is the output current. In a typical notebook system, the battery rail decoupling is achieved by using MLC capacitors or a mixture of MLC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by eight pieces of 10 mF, 25 V MLC capacitors, with a ripple current rating of about 1.5 A each.
RC Snubber
TTSNS R CTT RTH1
ADP3212
Figure 33. Single-Point Thermal Monitoring
It is important in any buck topology to use a resistor-capacitor snubber across the low side power MOSFET. The RC snubber dampens ringing on the switch node when the high side MOSFET turns on. The switch node ringing could cause EMI system failures and increased stress on the power components and controller. The RC snubber should be placed as close as possible to the low side MOSFET. Typical values for the resistor range from 1 W to 10 W. Typical values for the capacitor range from 330 pF to 4.7 nF. The exact value of the RC snubber depends on the PCB layout and MOSFET selection. Some fine tuning must be done to find the best values. The equation below is used to find the starting values for the RC subber.
R Snubber + 2 p 1 f Ringing C OSS
(eq. 36)
To monitor the temperature of multiple-point hot spots, use the configuration shown in Figure 34. If any of the monitored hot spots reaches the alarm temperature, the VRTT signal is asserted. The following calculation sets the alarm temperature:
1 2) R TTSET1 + 1 2* VFD VREF VFD VREF
(eq. 39)
R TH1AlarmTemperature
where VFD is the forward drop voltage of the parallel diode. Because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mV. Assuming the same conditions used for the single-point thermal monitoring example--that is, an alarm temperature of 100C and use of an NTHS-0603N011003J Vishay thermistor--solving Equation 39 gives a RTTSET of 7.37 kW, and the closest standard resistor is 7.32 kW (1%).
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ADP3212A, NCP3218A
5V VCC 37 ADP3212 VRTT - + R CTT R TTSNS 11 RTH1 RTTSET3 RTTSET1 RTTSET2
7. Measure the output ripple with no load and with a full load with scope, making sure both are within the specifications.
Set the AC Load Line
RTH3 RTH2
Figure 34. Multiple-Point Thermal Monitoring
The number of hot spots monitored is not limited. The alarm temperature of each hot spot can be individually set by using different values for RTTSET1, RTTSET2, ... RTTSETn. Tuning Procedure for APD3212A/NCP3218A
Set Up and Test the Circuit
1. Build a circuit based on the compensation values computed from the design spreadsheet. 2. Connect a dc load to the circuit. 3. Turn on the APD3212A/NCP3218A and verify that it operates properly. 4. Check for jitter with no load and full load conditions.
Set the DC Load Line
1. Remove the dc load from the circuit and connect a dynamic load. 2. Connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 ms/div. 3. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 4. Measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). Try to use a vertical scale of 100 mV/div or finer. 5. The resulting waveform will be similar to that shown in Figure 35. Use the horizontal cursors to measure VACDRP and VDCDRP, as shown in Figure 35. Do not measure the undershoot or overshoot that occurs immediately after the step.
1. Measure the output voltage with no load (VNL) and verify that this voltage is within the specified tolerance range. 2. Measure the output voltage with a full load when the device is cold (VFLCOLD). Allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (VFLHOT). If the difference between the two measured voltages is more than a few millivolts, adjust RCS2 using Equation 40.
R CS2(NEW) + R CS2(OLD) V NL * V FLCOLD (eq. 40) V NL * V FLHOT
VACDRP
VDCDRP
Figure 35. AC Load Line Waveform
3. Repeat Step 2 until no adjustment of RCS2 is needed. 4. Compare the output voltage with no load to that with a full load using 5 A steps. Compute the load line slope for each change and then find the average to determine the overall load line slope (ROMEAS). 5. If the difference between ROMEAS and RO is more than 0.05 mW, use the following equation to adjust the RPH values:
R PH(NEW) + R PH(OLD) R OMEAS RO
(eq. 41)
6. If the difference between VACDRP and VDCDRP is more than a couple of millivolts, use Equation 42 to adjust CCS. It may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason).
C CS(NEW) + C CS(OLD) V ACDRP V DCDRP
(eq. 42)
6. Repeat Steps 4 and 5 until no adjustment of RPH is needed. Once this is achieved, do not change RPH, RCS1, RCS2, or RTH for the rest of the procedure.
7. Repeat Steps 5 and 6 until no adjustment of CCS is needed. Once this is achieved, do not change CCS for the rest of the procedure. 8. Set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning VACDRP and VDCDRP are equal. 9. Ensure that the load step slew rate and the powerup slew rate are set to ~150 A/ms to 250 A/ms (for example, a load step of 50 A should
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ADP3212A, NCP3218A
take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive overshoot at powerup if a minimum current is incorrectly set (this is an issue if a VTT tool is in use).
Set the Initial Transient
VTRANREL VDROOP
1. With the dynamic load set at its maximum step size, expand the scope time scale to 2 ms/div to 5 ms/div. This results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after VDROOP (see Figure 36).
Figure 37. Transient Setting Waveform, Load Release Layout and Component Placement
VDROOP
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
VTRAN1
VTRAN2
Figure 36. Transient Setting Waveform, Load Step
2. If both overshoots are larger than desired, try the following adjustments in the order shown. a. Increase the resistance of the ramp resistor (RRAMP) by 25%. b. For VTRAN1, increase CB or increase the switching frequency. c. For VTRAN2, increase RA by 25% and decrease CA by 25%. If these adjustments do not change the response, it is because the system is limited by the output decoupling. Check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. For load release (see Figure 37), if VTRANREL is larger than the value specified by IMVP-6.5, a greater percentage of output capacitance is needed. Either increase the capacitance directly or decrease the inductor values. (If inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures).
1. For best results, use a PCB of four or more layers. This should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 mW at room temperature. 2. When high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. If critical signal lines (including the output voltage sense lines of the APD3212A/NCP3218A) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. An analog ground plane should be used around and under the APD3212A/NCP3218A for referencing the components associated with the controller. This plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane.
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ADP3212A, NCP3218A
5. The components around the APD3212A/NCP3218A should be located close to the controller with short traces. The most important traces to keep short and away from other traces are those to the FB and CSSUM pins. Refer to Figure 30 for more details on the layout for the CSSUM node. 6. The output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. 7. Avoid crossing signal lines over the switching power path loop, as described in the Power Circuitry section. 8. Connect a 1 mF decoupling ceramic capacitor from VCC to GND. Place this capacitor as close as possible to the controller. Connect a 4.7 mF decoupling ceramic capacitor from PVCC to PGND. Place capacitor as close as possible to the controller.
Power Circuitry
the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer heat to the surrounding air. To achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the MOSFETs on the opposite side of the PCB. In addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. For best EMI containment, a solid power ground plane should be used as one of the inner layers and extended under all power components.
Signal Circuitry
1. The switching power path on the PCB should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power-converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. 2. When a power-dissipating component (for example, a power MOSFET) is soldered to a PCB,
1. The output voltage is sensed and regulated between the FB and FBRTN pins, and the traces of these pins should be connected to the signal ground of the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. Therefore, the FB and FBRTN traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCORE common node for the inductors of all the phases. 3. On the back of the APD3212A/NCP3218A package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the APD3212A/NCP3218A is not recommended because the metal pad may cause shorting between vias.
ORDERING INFORMATION
Device Number* ADP3212AMNR2G NCP3218AMNR2G Temperature Range -40C to 100C -40C to 100C Package 48-Lead Frame Chip Scale Pkg [QFN_VQ] 7x7 mm, 0.5 mm pitch 48-Lead Frame Chip Scale Pkg [QFN_VQ] 6x6 mm, 0.4 mm pitch Package Option CP-48-1 CP-48-1 Shipping 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *The "G'' suffix indicates Pb-Free package.
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ADP3212A, NCP3218A
PACKAGE DIMENSIONS
QFN48 7x7, 0.5P CASE 485AJ-01 ISSUE O
D
PIN 1 LOCATION
AB
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO THE PLATED TERMINAL AND IS MEASURED ABETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 7.00 BSC 5.00 5.20 7.00 BSC 5.00 5.20 0.50 BSC 0.20 --- 0.30 0.50
2X
0.15 C
2X
0.15 C 0.05 C 0.08 C
NOTE 4
DETAIL A 13 12
48X
L
EEE EEE EEE
TOP VIEW (A3) A1 SIDE VIEW D2
25
E L
DETAIL A OPTIONAL CONSTRUCTION 2X SCALE
A C
SEATING PLANE
K
SOLDERING FOOTPRINT*
5.20 1 E2
2X 2X
7.30
1 48 37
36
0.63 b 0.10 C A B 0.05 C
NOTE 3
48X
e e/2 BOTTOM VIEW
48X
0.30
48X
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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ADP3212A, NCP3218A
PACKAGE DIMENSIONS
QFN48 6x6, 0.4P CASE 485AN-01 ISSUE O
D
PIN ONE LOCATION
AB L1
L
L
E
ALTERNATE TERMINAL CONSTRUCTIONS
DETAIL A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.15 0.25 6.00 BSC 4.25 4.55 6.00 BSC 4.25 4.55 0.40 BSC 0.20 MIN 0.35 0.55 0.00 0.15
2X 2X
0.15 C
0.15 C 0.10 C 0.08 C
TOP VIEW
DETAIL B
(A3)
A
A1 SIDE VIEW C K
SEATING PLANE
NOTE 4
DETAIL A 13
D2
25
E2 L
1
e
40
37 48X
e/2 BOTTOM VIEW
b 0.10 C A B 0.05 C
NOTE 3
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EEE EEE
DETAIL B
EEEE EEEE EEEE EEEE
EXPOSED Cu
MOLD CMPD
ALTERNATE CONSTRUCTION
SOLDERING FOOTPRINT*
6.40 4.56 0.73
48X
4.56
6.40
0.40 PITCH
0.25
DIMENSIONS: MILLIMETERS
48X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ADP3212A/D

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